Stability of Amorphous Silicon Thin Film Transistors and Circuits

iHydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) have been widely used forthe active-matrix addressing of flat panel displays, optical scanners and sensors. Extending theapplication of the a-Si TFTs from switches to current sources, which requires continuousoperation such as for active-matrix organic light-emitting-diode (AMOLED) pixels, makesstability a critical issue. This thesis first presents a two-stage model for the stability characterization and reliable lifetimeprediction for highly stable a-Si TFTs under low gate-field stress. Two stages of the thresholdvoltage shift are identified from the decrease of the drain saturation current under low-gate field.The first initial stage dominates up to hours or days near room temperature. It can becharacterized with a stretched-exponential model, with the underlying physical mechanism ofcharge trapping in the gate dielectric. The second stage dominates in the long term and thensaturates. It corresponds to the breaking of weak bonds in the amorphous silicon. It can bemodeled with a “unified stretched exponential fit,” in which a thermalization energy is used tounify experimental measurements of drain current decay at different temperatures into a singlecurve. Two groups of experiments were conducted to reduce the drain current instability of a-Si TFTsunder prolonged gate bias. Deposition conditions for the silicon nitride(SiNx) gate insulator andthe a-Si channel layer were varied, and TFTs were fabricated with all reactive ion etching steps,or with all wet etching steps, the latter in a new process. The two-stage model that unites chargetrapping in the SiNx gate dielectric and defect generation in the a-Si channel was used to interpretthe experimental results. We identified the optimal substrate temperature, gas flow ratios, and RFdeposition power densities. The stability of the a-Si channel depends also on the depositionconditions for the underlying SiNx gate insulator. TFTs made with wet etching are more stablethan TFTs made with reactive ion etching. Combining the various improvements raised theextrapolated 50% decay time of the drain current of back channel passivated dry-etched TFTsunder continuous operation at 20°C from 3.3 × 104sec (9.2 hours) to 4.4 × 107sec (1.4 years).The 50% lifetime can be further improved by ~2 times through wet etching process. Two assumptions in the two-stage model were revisited. First, the distribution of the gap statedensity in a-Si was obtained with the field-effect technique. The redistribution of the gap statedensity after low-gate field stress supports the idea that defect creation in a-Si dominates in thestract